What could be the reason for the missing write response Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP configured in non-AXI back-pressure mode? - What could be the reason for the missing write response Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP configured in non-AXI back-pressure mode? Description Due to a problem in the Intel® Quartus® Prime Pro software version 21.4 and 22.1, data loss on the write response path in non-AXI backpressure mode is expected when AXI backpressure is not enabled in Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP, write responses may be lost. The reason is that the fabric can potentially receive two write responses in a single cycle. In non-backpressure mode, there is only a cycle’s worth of read response buffering. Data loss occurs when there are two back-to-back cycles in which a pair of write responses is received. The issue is most prevalent when the fabric clock is relatively low. Even though that reduces the write command rate at the interface, if a refresh cycle causes a lot of write commands to be buffered by the Intel® Stratix® 10 MX/NX FPGA device BMC devices, there will be a corresponding flood of responses once the refresh has completed. To work around this problem, Added internal FIFO for each pseudo-channel which has negligible impact on the area. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.2 onwards. Custom Fields values: ['novalue'] Troubleshooting 14016252889 False ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software'] 22.2 21.4 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']