Why is my Cyclone V or Stratix V Altera_PLL reset port is inverted in simulation? - Why is my Cyclone V or Stratix V Altera_PLL reset port is inverted in simulation? Description Due to a problem in the Quartus ® II software version 13.1, you see the the Altera PLL reset port is inverted in gate level simulation. This problem occurs in Cyclone® V or Stratix® V designs when advanced mode or reconfiguration is enabled in the Altera_PLL. Resolution To work around this problem in ModelSim, add the following switch to the vlog command define POSTFIT_SIM_USE_ICD_PLL_MODEL For example add the following lines to the *_run_msim_gate_verilog.do file For Cyclone V designs vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/mentor/cyclonev_*.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/cyclonev_atoms.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL For Stratix V designs vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/mentor/stratixv_*.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/stratixv_atoms.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_primitives.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_lnsim.sv vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/220model.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/sgate.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_mf.v vsim -t 1ps transport_int_delays transport_path_delays -voptargs= acc gate_work.<top_level_design.vho/vo> Related Articles Why does the Altera PLL IP signal phase_done not assert in gate-level simulation of dynamic phase shift? Custom Fields values: ['novalue'] Troubleshooting novalue False ['Reset'] ['novalue'] novalue novalue ['Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']