How do I calculate the value of the static timing adjustment registers of the Low Latency Ethernet 10G MAC MegaCore? - How do I calculate the value of the static timing adjustment registers of the Low Latency Ethernet 10G MAC MegaCore? Description To calculate the value of the static timing adjustment registers it is necessary to convert the TX/RX PMA delay to hexadecimal and set it to associated static timing adjustment register such as tx_ns_adjustment_10G of the Low Latency Ethernet 10G MAC MegaCore®. Example for Arria V GZ 40-bits PMA mode: Find the PMA delay in the Low Latency Ethernet 10G MAC MegaCore user guide 10G hardware digital Tx delay = 123 UI x 0.097 ns = 11.931 ns 10G hardware analog Tx delay = -1.1 ns Calculate the total delay 11.931 ns - 1.1 ns = 10.831 ns Convert the nanoseconds to hexadecimal 10 ns = 0x000A Multiply the fractional nanoseconds by 65,536 (0x10000) 0.831 ns x 65,536 = 54,460.416 Round the multiplied fractional nanoseconds to unit 54,460.416 => 54,460 Convert the rounded fractional nanoseconds to hexadecimal 54,460 = 0xD4BC Set the converted delay value to associated register tx_ns_adjustment_10G = 0x000A tx_fns_adjustment_10G = 0xD4BC Custom Fields values: ['novalue'] Troubleshooting novalue False ['Ethernet'] ['novalue'] novalue novalue ['Arria® V GZ FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']