What happens to p_clk, core_clk_out, and Avalon interface width when the PCIe core down-trains? - What happens to p_clk, core_clk_out, and Avalon interface width when the PCIe core down-trains? Description The PCI Express® core always operates as specified in the original configuration. The core_clk_out and Avalon® Interface width remain unchanged. For example, assuming the Hard IP PCIe core is configured as Gen2x8, with pclk=500MHz, core_clk_out=250MHz, and Avalon width=128. If it is down-trained to Gen1x1, it will operate in Gen1 settings with pclk=250MHz, core_clk_out=250MHz, and Avalon width=128. Resolution The above description applies to both Hard IP and Soft IP. Custom Fields values: ['novalue'] Troubleshooting NA False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® IV GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']