Qsys Generates Vid_Std Signal Even When Option is Turned Off - Qsys Generates Vid_Std Signal Even When Option is Turned Off Description Qsys always generates the vid_std signal for the Clocked Video Input II IP core, even when you do not turn on the Use vid_std bus option. The vid_std signal is sampled and stored in the Standard register of the IP core to be read back for software control. Resolution If you do not need this signal, leave the input disconnected at the instancing of the Qsys system. This issue will be fixed in a future version of the Clocked Video Input II IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']