Eliminating Barriers to Hyper-Retiming - 35 Minutes Hyper-Retiming in the Quartus® Prime Pro software is a key to your FPGA designs reaching the highest performance in FPGAs built using the Altera® Hyperflex ® architecture. In the Eliminating Barriers to Hyper-Retiming course, you learn the circuit situations that prevent the Hyper-Retimer module from using Agilex™ and Stratix® 10 FPGA Hyper-Registers to increase your design performance. You will also learn various design modifications and constraints you can implement that will help you to circumvent these barriers to Hyper-Retiming. Finally, you will see how to use the Fast Forward analysis tool to take the guesswork out of this process, guiding you to the target retiming restrictions that could be removed to increase your designs clock speed. Course Objectives At course completion, you will be able to: Describe the design structures that prevent Hyper-Retiming Make RTL changes to eliminate Hyper-Retiming restrictions Use Fast Forward analysis to determine which restrictions should Be removed Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Quartus Prime Pro design software Familiarity with Verilog or VHDL synthesizable design structures Familiarity with the Hyperflex architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10EHYPRET. FPGA_OS10EHYPRET. <p>Eliminating Barriers to Hyper-Retiming</p>