get register driven clock name - get register driven clock name How to get clock name on which the register is running in Q std?solved only using get_path, but during synthesis I get an error because get_path is not from sdc or sdc_ext package Replies: Re: get register driven clock name i found solution: https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/timinganalyzer/exm-tq-clocks-feeding-register.html Replies: Re: get register driven clock name We do not receive any response from you to the previous answer that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. Replies: Re: get register driven clock name Any further queries? Replies: Re: get register driven clock name i read back that you mention that your top will be use in different project. Unfortunately, you will have to still make use of the same style that mention below. In each of your different project, you need to create clock first, and create_generated clock to your top module. One things for you to explore is to try tcl scripts, otherwise, you will have to do it manually in each different project, Replies: Re: get register driven clock name when you mention on top, do you mean the top level of the module? Why there is no access to it? Replies: Re: get register driven clock name yes, but clkA and clkB on Top, to which I have no access and I do not know anything about it Replies: Re: get register driven clock name Is this the multiplexer that you are working at? https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/timinganalyzer/exm-tq-clock-mux.html Replies: Re: get register driven clock name My multiplexer switches the clock. And to describe it, you need to describe the clock groups Replies: Re: get register driven clock name Usually, Multiplexer does not consist of a clock. Does your Mux have a clock? If no, you do not need to set any clock for it. Timing analyzer analyze the path from register to register, once you have a register, you should have a clock to be constraint. Replies: Re: get register driven clock name Ok, how to describe this multiplexer correctly? But "my module" must be used in different projects, and i don't know whats clocks used on "Tol level" Replies: Re: get register driven clock name any update? Replies: Re: get register driven clock name Can you describe more on the previous question? Once you set multicylce, you should be able to open up timing analyzer to analyze for that path. Replies: Re: get register driven clock name that is, there is no analog of entity-bound SDC files for quartus std? Replies: Re: get register driven clock name True, but the GUI dialog boxes make it easy to form SDC constraints with correct syntax and they're the only way to get to the Name Finder. Replies: Re: get register driven clock name even worse, I don't need a graphical interface. i want to describe in sdc Replies: Re: get register driven clock name I think multicycle is just being given as an example of accessing one of the GUI dialog boxes to access the Name Finder tool. There's no way to search for nodes in the timing netlist without going through one of these dialog boxes and I guess multicycle was selected just as an example. You don't need multicycle for the design. Replies: Re: get register driven clock name Yes, how does set_multicycle_path help me do my path analysis correctly? Replies: Re: get register driven clock name any further queries? Replies: Re: get register driven clock name It will be still the same, have to try to look for nodes by: Timing analyzer -> Constrain -> set_multiclycle_path -> select the nodes Replies: Re: get register driven clock name What if I don't have access to the main design? Replies: Re: get register driven clock name If you want to name the clocks differently for timing analysis, in your clock constraints (create_clock or create_generated_clock), use the -name option. This won't change their names in the design, however. Replies: Re: get register driven clock name set_clock_groups -physically_exclusive -group [get_clocks {clk}] -group [get_clocks {vidi_clock}] however, in the toplevel file, these clocks are named differently. And I would like to use this module in other projects. That is, create an IP core and just use Replies: Re: get register driven clock name To find the correct nodes, what you can do is go to Timing analyzer -> Constrain -> set_multiclycle_path -> select the nodes that you want. Replies: Re: get register driven clock name I am describing a module in which there are several clock signals, and several instances of this module are planned, operating at different frequencies. I am going to make a qip file with source code and SDS file, in which I want to describe data for correct time analysis. I would also like this description to be correctly taken into account by fitter Replies: Re: get register driven clock name where do you plan to put this get_register? Are you planning to put it in *.sdc? If yes, you may have to run timing analyzer to get the correct nodes.