What is the correct order of DW header in PCIe err_desc_func0 bus? - What is the correct order of DW header in PCIe err_desc_func0 bus? Description The correct order of DW header in err_desc_func0 is: err_desc_func0[127:0] = {header0, header1, header2, and header3}; Where: * Header0 = 1st DW => Header Byte0, Header Byte1, Header Byte2, Header Byte3 * Header1 = 2nd DW => Header Byte4, Header Byte5, Header Byte6, Header Byte7 * Header2 = 3rd DW => Header Byte8, Header Byte9, Header Byte10, Header Byte11 * Header3 = 4th DW => Header Byte12, Header Byte13, Header Byte14, Header Byte15 Note: Header 3 is only applicable for four DW header format. The above rule is valid for all devices that support PCIe ® core including S4GX, A2GX, and C4GX. It is also applied for both soft IP and hard IP. Resolution Some updates to formatting: The correct order of DW header in err_desc_func0 is: err_desc_func0[127:0] = {header0, header1, header2, and header3}; Where: * Header0 = 1st DW => {Header Byte0, Header Byte1, Header Byte2, Header Byte3} * Header1 = 2nd DW => {Header Byte4, Header Byte5, Header Byte6, Header Byte7} * Header2 = 3rd DW => {Header Byte8, Header Byte9, Header Byte10, Header Byte11} * Header3 = 4th DW => {Header Byte12, Header Byte13, Header Byte14, Header Byte15} Note: Header 3 is only applicable for four DW header format. The above rule is valid for all devices that support PCIe core including S4GX, A2GX, and C4GX. It is also applied for both soft IP. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0 novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® IV GX FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']