Why does the tx_pll_locked port fail to assert on the Intel Agilex® 7 F-Tile PMA-based high-speed IP after dynamically reconfiguring the channel to another profile? - Why does the tx_pll_locked port fail to assert on the Intel Agilex® 7 F-Tile PMA-based high-speed IP after dynamically reconfiguring the channel to another profile? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, the tx_pll_locked port of an Intel Agilex® 7 F-Tile PMA-based high-speed IP may fail to assert after dynamically reconfiguring the channel to another profile. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, install the following patch: Intel® Quartus® Prime Pro Edition Software v23.3 Patch 0.22fw for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v23.3 Patch 0.22fw for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v23.3 Patch 0.22fw (.txt) This problem has been fixed in release 23.4 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14020708063 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']