Hyper-Optimization Techniques 2: Pre-Computation - Click the ENROLL button near the top of the screen to play this eLearning. 9 Minutes Are you targeting a Stratix® 10 device and wanting to learn how your design can reach the maximum core performance? This is the 2nd of 3 online courses that teaches advanced optimization techniques for the Stratix® 10 HyperFlex™ Architecture. In this course, you will learn to use pre-computation techniques to shrink critical chain loops to achieve breakthrough levels of operating clock frequency (fmax) in your design thus unleashing the full potential of the Stratix® 10 Hyperflex architecture. Note: While the focus of this course is the Stratix® 10 device family, many of the techniques you will learn can be used to improve performance in other device architectures. Course Objectives At course completion, you will be able to: Learn the Hyper-optimization restructuring technique of moving loops from feedback to feedforward Reduce loop size to lessen the impact on Hyper-Retiming Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Quartus® II design software Familiarity with Verilog or VHDL synthesizable design structures If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the notes section of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10PRECOMP. FPGA_OS10PRECOMP. <p>Hyper-Optimization Techniques 2: Pre-Computation</p>