Why do I see errors on IO banks in HPS first mode on Stratix® 10 and Agilex™ 7 SoC FPGAs? - Why do I see errors on IO banks in HPS first mode on Stratix® 10 and Agilex™ 7 SoC FPGAs? Description Due to a problem in Secure Device Manager (SDM) fimrware of Quartus® Prime Pro Edition Software version 23.2 and eariler, you may see errors on the IO banks when using HPS first mode. The Hard Processor System (HPS) may crash if impacted IO banks are accessed during boot up or Phase 2 configuration of the FPGA from HPS. Resolution This problem has been fixed with Quartus® Prime Pro Edition Software version 23.4 for Stratix® 10 SoC FPGAs and 23.3 for Agilex™ 7 SoC FPGAs. Custom Fields values: ['novalue'] Troubleshooting 13012081040 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 22.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']