IntelliProp AES Encryption with XTS IP Core (IPC-BL120A-ZM) - The "Commander" of data-at-rest security; a high-performance AES-XTS encryption/decryption IP core specifically architected for sector-based block storage protection in FPGA-based SSD controllers and… IntelliProp is the industry's Strategic Gatekeeper for high-assurance memory and data storage. We provide "Gold Standard" IP cores and expert design services for NVMe, SATA, SAS, and AES-XTS security… Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® V GX FPGA Cyclone® V SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA In the world of high-capacity storage, protecting the physical media is the last line of defense. The IPC-BL120A-ZM stands as the industry's "Commander" of secure data-at-rest, utilizing the AES-XTS (XEX Tweakable Block Cipher with Ciphertext Stealing) mode. Unlike standard AES modes, XTS is specifically designed for block storage, using a "tweak" based on the logical block address (LBA) to ensure that the same data stored in different locations results in unique ciphertext. This core allows engineers to implement FIPS-compliant, hardware-based encryption that is fully transparent to the host. It is specifically engineered to handle the unique requirements of sector-based storage—including the ability to handle data units that are not a multiple of the block size—ensuring that every byte of a drive is secured without the overhead of software-level encryption. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation Wireless IntelliProp AES Encryption with XTS IP Core (IPC-BL120A-ZM) Key Features Algorithm: NIST and IEEE compliant AES-XTS mode. Offering Brief Yes Yes No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® V GX FPGA Cyclone® V SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Agilex™ 7 FPGA Starter Kit Yes 25.3.0 Offering Brief Production a1JUi0000049UFKMA2 What's Included Encrypted Verilog RTL Ordering Information IPC-BL120-ZM a1JUi0000049UFKMA2 Production Intellectual Property (IP) a1MUi00000BO8sHMAT a1MUi00000BO8sHMAT Select 2026-04-28T20:43:01.000+0000 The "Commander" of data-at-rest security; a high-performance AES-XTS encryption/decryption IP core specifically architected for sector-based block storage protection in FPGA-based SSD controllers and drive-level security modules. Partner Solutions