Power-Down Entry Command Timing Violation - Power-Down Entry Command Timing Violation Description ALTMEMPHY-based designs created with a version of the high-performance controller (HPC II) earlier than 11.0, with the Enable Auto Power Down option turned on, violate refresh to precharge command timing, breaching JEDEC requirement. This issue affects all designs created in a pre-11.0 version of HPC II, with the Enable Auto Power Down option turned on. Your design fails to simulate and doesn’t work in hardware. Resolution To meet the JEDEC requirement, perform the following steps: Open the alt_ddrx_bank_timer.v file. Locate the following command: always @ (*) begin cs_can_power_down [w_cs] = power_saving_enter_ready [w_cs] & chip_idle; end and change to: always @ (posedge ctl_clk or negedge ctl_reset_n) begin if (!ctl_reset_n) cs_can_power_down [w_cs] <= 1\'b0; else cs_can_power_down [w_cs] <= power_saving_enter_ready [w_cs] & chip_idle; end This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']