How to constrain virtual pins for timing analysis in the Quartus® Prime Software? - How to constrain virtual pins for timing analysis in the Quartus® Prime Software? Description In the Quartus® Prime Software, the Timing Analyzer uses a 0ns clock insertion delay for virtual pins since they do not have an associated clock. This results in a large clock skew between the source and destination clock paths. Resolution To avoid this timing violation, perform one of the following two options: Create a register wrapper design around the virtual pin so that it has an associated clock. In the Quartus® Prime Pro Edition Software version 17.1 and later, you can use the constraints below: Virutal pin as an input port: set_input_delay -clock <clock port> -add_delay <delay> <virtual input pin> -reference_pin <the clock pin of the register that feeds the input port> Virutal pin as an output port: set_output_delay -clock <clock port > -add_delay <delay> <virtual output pin> -reference_pin <the clock pin of the register that feeds the output port> Custom Fields values: ['novalue'] Troubleshooting 1408167010 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 18.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']