Clock Domain Crossing Considerations - Same Course in Japanese: クロック・ドメイン・クロッシングの考慮事項 21 Minutes This course presents some considerations when crossing clock domains in Altera® FPGAs. The course reviews metastability and synchronizer circuits, goes over the CDC Viewer reporting tool found in Altera® Quartus® Pro Software Timing Analyzer, and uses a simple design to cross clock domains. Course Objectives At course completion, you will be able to: Use the CDC Viewer in timing Analyzer Analyze clock domain crossing designs Constrain clock domain crossing designs Skills Required Familiarity with Altera® Quartus Prime Pro software Familiarity with timing Analyzer If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSWCDCC. FPGA_ODSWCDCC. <p>Clock Domain Crossing Considerations</p>