How to instantiate components of Cyclone V IOE for design. - How to instantiate components of Cyclone V IOE for design. Hello, I am trying to instantiate the DDR and read FIFO items that are integrated into the Cyclone V I/O elements (IOEs). I know you can instantiate DDR registers using the ALTDDIO IP. However, I have not been able to find any way to instantiate the READ FIFO that is attached to the output of the DDR registers. How can I instantiate the Read FIFO? This is an image from the Cyclone V's Volume 1 User Guide: Device Integration and Interfaces. you can see at the bottom is the DDR registers and attached to the output is a block labeled "Read FIFO". Thank you, Tucker Z Replies: Re: How to instantiate components of Cyclone V IOE for design. Hi Tucker, There is step to infer fifo manually that might be help for you design to link at ddr output. You may look at below documents. https://www.intel.com/content/www/us/en/docs/programmable/683082/22-3/inferring-fifos-in-hdl-code.html Replies: Re: How to instantiate components of Cyclone V IOE for design. Hi Tucker, This is true as mentioned by sstrell. In this case place and route engine will automatically choose the resources needed to implement a design. But to implement the fifo read to output of DDR, I am checking if that is possible or not by manually instantiating it. Replies: Re: How to instantiate components of Cyclone V IOE for design. Perhaps someone at Intel can shed some more light on this. Replies: Re: How to instantiate components of Cyclone V IOE for design. Don't know. Like I said, it's possible a particular IP might have an option you could set to enable its use, but the whole point of a place and route engine is to automatically choose the resources needed to implement a design. Replies: Re: How to instantiate components of Cyclone V IOE for design. So they only way to use that FIFO is to have the software infer its usage? Replies: Re: How to instantiate components of Cyclone V IOE for design. Structures like that are usually added as needed based on the design. If you add a FIFO IP and connect it to an I/O or use an IP that has a parameter for using the FIFO, the synthesized design would make use of that hardware. There's no specific IP as far as I know to implement that particular FIFO.