Why are the fPLL C counters not updated correctly when dynamically reconfiguring an Altera_PLL using the Altera_PLL_Reconfig IP? - Why are the fPLL C counters not updated correctly when dynamically reconfiguring an Altera_PLL using the Altera_PLL_Reconfig IP? Description When using Altera_PLL_Reconfig, the translation logic from C logical counter to C physical counter may map incorrectly in the Quartus® II software versions 13.1 and earlier, causing the IP to reconfigure the wrong physical counter. Resolution Disable the ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP assignment in your project. Current versions of the Quartus II software must have this assignment disabled in order for C output counters to be updated dynamically. The IP is scheduled to be enhanced in a future version of the Quartus II software to allow you to use the ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP assignment and dynamic reconfiguration of the C output counters. You can refer to AN 661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions (PDF). Related Articles How do I prevent PLL output counter merging in Quartus II 12.1 and later for Stratix V, Arria V and Cyclone V devices? Error (15629): Atom comb~0 is dependent on unconnected input ports What is the correct C counter location assignment to be used when performing PLL Dynamic Phase Shifting with the Altera_PLL megafunction for 28nm devices? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']