Compilation Error in DisplayPort Receiver - Compilation Error in DisplayPort Receiver
Description The compilation of the DisplayPort IP core receiver generates the following error for 1- and 2-lane instantiations: Error (10232): Verilog HDL error at bitec_dp_rx_decoder.v(2262): index 45 cannot fall outside the declared range [29:0] for vector "dp_rx_ber_cntr_av" This issue is fixed in version 14.1 of the DisplayPort IP core.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
14.1
14.0
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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