How do I simulate Stratix V designs in VHDL using the ModelSim-Altera Starter Edition software? - How do I simulate Stratix V designs in VHDL using the ModelSim-Altera Starter Edition software? Description Due to a problem in the ModelSim-Altera Starter Edition software versions 6.6c and 6.6d, designs in VHDL targeting Stratix® V devices cannot be simulated. This problem does not affect the ModelSim-Altera Edition software. These versions of the ModelSim-Altera Starter Edition are provided with the Altera Complete Design Suite versions 10.1 and 11.0. Due to this problem, you may see errors such as the following: # ALTERA version supports only a single HDL # ** Fatal: (vsim-3612) Instantiation of 'stratixv_ds_coef_sel' failed. Unable to check out Verilog simulation license. Resolution To work around this problem, use one of the following options: Simulate your design targeting Stratix V devices using Verilog HDL. Simulate your design targeting Stratix V devices using the ModelSim-Altera Edition software. This problem is fixed beginning with the ModelSim-Altera Starter Edition software version 10.0c provided with the Altera Complete Design Suite version 11.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 11.1 10.1 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']