How to report propagation delay from pin to pin with just combinational logic in between - How to report propagation delay from pin to pin with just combinational logic in between The title basically says it all. If I have just combinational logic between two FPGA pins how can I report the propagation delay of that path in timing analyzer? "report_timing -from [get_ports {input_pin}] -to [get_ports {output_pin}]" results in the message "Report Timing: No setup paths were found" Am I doing something wrong or is there another way? Thanks! Replies: Re: How to report propagation delay from pin to pin with just combinational logic in between Hi, This constraint could not be used for pin to pin, you have to use report_path instead. Please check the following chapter: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_sdctmq.pdf#page=140 Regards. Replies: Re: How to report propagation delay from pin to pin with just combinational logic in between That's not a constraint, it's a reporting command. OP should still be able to use report_timing. You have to have some constraints on the I/O. The best and easiest way to do this with with set_max_delay and set_min_delay. If the I/O show up as unconstrained in the unconstrained paths report, report_timing won't work. Once the I/O are constrained, report_timing as you mentioned should work. Replies: Re: How to report propagation delay from pin to pin with just combinational logic in between Hi, This constraint could not be used for pin to pin, you have to use report_path instead. Please check the following chapter: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_sdctmq.pdf#page=140 Regards.