CPRI IP Core Variations That Target a Stratix V Device Do Not Achieve Timing Closure - CPRI IP Core Variations That Target a Stratix V Device Do Not Achieve Timing Closure Description CPRI IP core variations that target a Stratix V device fail to achieve timing closure with the default Quartus II Fitter settings. Specifically, they experience hold time violations on the RAM input path. Resolution To achieve better timing closure results, perform one of the following actions: Add set_min_delay assignments to overconstrain timing. Try different Quartus II Fitter seeds. This issue will be fixed in a future version of the CPRI MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']