Why does the Arria 10 nPOR input not keep the PCIe IP in reset? - Why does the Arria 10 nPOR input not keep the PCIe IP in reset? Description When using Quartus ® Prime software versions 16.0 and later, the Arria ® 10 PCI Express ® Hard IP npor signal does not reset the HIP when driving a 0 or 1. Resolution As a work around in v16.0 the RTL can be modified to enable a user side reset, by making the change below. Change the USE_ALTPCIE_RS_HIP_LOGIC =1 , module "<variant>_altera_pcie_a10_hip_<letters>.v This problem will be fixed in a future release of the Quartus software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']