Why Intel® Cyclone® V GT Development Kit failed configuration with compression enabled? - Why Intel® Cyclone® V GT Development Kit failed configuration with compression enabled? Description Intel® Cyclone® V GT Development Kit will fail to be configured when using compressed bitstream in the flash due to Intel® MAX®V has tied one of the MSEL bit to 0. Resolution Modify the Intel® Max® V design on pfl_control.vhd which is under the "hdl" folder from the Development Kit installation folder. Go to line 397, you will observe (msel <= "ZZZ0Z";). Change it to (msel <= "ZZZZZ";). This will enable the MSEL to be selected according to the DIPSW (DIP Switch) on the board. Ensure the correct MSEL selection according to its configuration mode. Custom Fields values: ['novalue'] Troubleshooting FB: 520159; False ['novalue'] ['novalue'] novalue novalue ['novalue'] ['novalue'] ['novalue'] ['novalue']