Why does the Triple-Speed Ethernet Intel® FPGA IP core with in 2xTBI PCS variant mode fail to detect Ethernet collisions? - Why does the Triple-Speed Ethernet Intel® FPGA IP core with in 2xTBI PCS variant mode fail to detect Ethernet collisions? Description Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.4 Software, the Triple-Speed Ethernet Intel® FPGA IP mii_col and led_col signals are not asserted when ethernet collision happens for the 2xTBI PCS variant when operating at 10Mbps or 100Mbps rate. Resolution There is no workaround for this problem. This problem is fixed starting from the Intel® Quartus® Prime Pro Edition v20.1 Software. Custom Fields values: ['novalue'] Troubleshooting 1507650988 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']