Where are the clocks for my Arria 10 Hard IP for PCI Express in Quartus II version 15.0 and later? - Where are the clocks for my Arria 10 Hard IP for PCI Express in Quartus II version 15.0 and later? Description Arria® 10 designs require strict adherence to the transceiver guidelines. For this reason derive_pll_clocks has been removed from the generated altpcied_a10.sdc . This file previously contained the following lines: # derive_pll_clock is used to calculate all clock derived from PCIe refclk # the derive_pll_clocks and derive clock_uncertainty should only # be applied once across all of the SDC files used in a project derive_pll_clocks -create_base_clocks derive_clock_uncertainty Resolution The above lines must now be included in your user created top level SDC. Please be sure to include those two lines. derive_pll_clocks -create_base_clocks derive_clock_uncertainty Custom Fields values: ['novalue'] Troubleshooting novalue False ['Basic Functions Clocks (Primary)'] ['novalue'] novalue novalue ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']