Error (175020): Illegal constraint of LVDS_CHANNEL that is part of Altera LVDS SERDES - Error (175020): Illegal constraint of LVDS_CHANNEL that is part of Altera LVDS SERDES Description You will receive this error if you are using Altera LVDS SERDES IP in Rx-CDR mode, with certain pin constraints in Arria® 10 and Cyclone® 10 GX devices. The Altera LVDS SERDES IP in Rx-CDR mode may only be placed on dedicated even numbered channels. Resolution To identify which pins may be used in Rx-CDR mode, refer to your device's Dedicated Tx/Rx Channel column of the pinout file. Only pin pairs with even numbers may be used. For example, LVDS2K_1 may not be used, and LVDS2K_2 can be used. Custom Fields values: ['novalue'] Troubleshooting FB: 493284; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] novalue 16.0 ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']