Why are the “rst_tx_stats” and the “rst_rx_stats” register bits not functioning correctly when using the F-tile Ethernet FPGA hard IP? - Why are the “rst_tx_stats” and the “rst_rx_stats” register bits not functioning correctly when using the F-tile Ethernet FPGA hard IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the rst_tx/rx_stats register may not get cleared after reset. Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and later, these register bits may not function correctly, and the resultant MAC TX Statistics and MAC RX Statistics might not be cleared correctly. Resolution You may need to assert and deassert these register bits multiple times as a workaround until the appropriate MAC Statistics are cleared correctly. There is no fix for this problem. Custom Fields values: ['novalue'] Troubleshooting 14023089448, 16024747034 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']