Fixed timing simulation of Stratix IV SERDES_RX - Fixed timing simulation of Stratix IV SERDES_RX
Description A bug in timing simulation of Stratix IV SERDES_RX was fixed, and, as a result, the timing simulation of SERDES_RX does not capture the data bit correctly. This issue does not affect silicon behavior. Resolution No workaround.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
10.1
10.0
['Stratix® IV FPGAs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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