AI Suite - Why does the Sequential IP not take a model argument? - AI Suite - Why does the Sequential IP not take a model argument? Hello Altera Community Why does the Sequential IP not take a model argument? When targeting the Spatial IP, there is an argument where you can input your model, which is an xml file (and a bin file), exported using OpenVino. Then it will convert these weights and such to .mif files for the FPGA to load. This is easy to understand. The Sequential IP is a lot harder to understand. I get that the architecture file does all the fpga block related configuration. But I don't understand how it will know which weights to use. Does the Sequential IP only work for the pre defined example graphs? Replies: Re: AI Suite - Why does the Sequential IP not take a model argument? Okay, it seems that this is only relevant when making a DDR free example 13.1. Generating Artifacts for On-Chip-Parameter Operation When a model is compiled with an architecture file that has the enable_on_chip_parameters FPGA AI Suite IP architecture file block configuration option enabled, the FPGA AI Suite compiler (dla_compiler) produces a set of memory initialization (.mif) files in a directory called on_chip_parameters under the export directory specified by the --dumpdir compiler command option. These files are required to build the bitstream for on-chip-parameter operation and to run software inference. You do not need to specify any additional compiler options when compiling an architecture with on-chip-parameter operation enabled. For an architecture with on-chip-parameter operation enabled (DDR-free or with DDR), the compiler produces the following files: ./ddrfree_filter_hw*.mifContain the model filters that are used to build the bitstream and update the model parameters via the CSR interface for on-chip-parameter operation. ./ddrfree_bias_scale_hw*.mifContain the model biases and scaling factors used to build the bitstream and update the model parameters via the CSR interface for on-chip-parameter operation ./ddrfree_filter_emu*.mifContain the model filters in software emulator form. ./ddrfree_bias_scale_emu*.mifContains the model biases and scaling factors in software emulator format ./ddrfree_config.mifStores the FPGA AI Suite instructions for the compiled model. These files are generated using the dla_compiler tool that takes the architecture definition (.arch file) and the target neural network model as inputs. The FPGA AI Suite Sequential IP requires a stream of instructions that describe the order in which convolutions, activations, and other operations are performed. This instruction stream is stored in a single .mif file (ddrfree_config.mif). You must also enable output streaming when using on-chip-parameter operation. The model must have a large enough stream buffer depth to accommodate all of the intermediate results during inference. Replies: Re: AI Suite - Why does the Sequential IP not take a model argument? It will not generate any files need to be included. It will only provide information what is the feature or layers that is not supported due it does not have such features in the IP. Replies: Re: AI Suite - Why does the Sequential IP not take a model argument? Okay so the dla compiler can be used to check that the OpenVino model can fit on the Sequential architecture description or it will report a mismatch. Will the dla compiler generate any files that need to be manually dragged into the IP repo generated by the dla create ip command? (For example in the spatial IP, the weight mif files will be placed somewhere deep inside the IP repo folder, and then I have to drag them into somewhere the Quartus compiler can find them.) Or are these files loaded into the FPGA after programming, if yes how is this done and what are the relevant files? Replies: Re: AI Suite - Why does the Sequential IP not take a model argument? Hi, The Sequential IP can support multiple model as it is depend on how you implement the features into the IP. So the flow is to run "dla_compiler --network-file model.xml --march my_arch.arch" where it report what is the unsupported layer in the current Sequential IP. Thanks.