VHDL IP Functional Simulation Fails - VHDL IP Functional Simulation Fails
Description When running the demonstration testbench with VHDL simulations, you receive the following error: Signal "wire_gnd" is type ieee.std_logic_1164.std_logic; expecting type ieee.std_logic_1164.std_logic_vector. This issue affects Stratix V receiver variants. There is no design impact. Resolution Use Verilog HDL simulations. This issue will be fixed in a future version of the POS-PHY Level 4 MegaCore function.
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
11.1
11.0
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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