Why does the system report completion timeout error and hang up when using Multi Channel DMA FPGA IP for PCI Express*? - Why does the system report completion timeout error and hang up when using Multi Channel DMA FPGA IP for PCI Express*? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, you might observe completion timeout error and system hang up when using Multi Channel DMA FPGA IP for PCI Express* when MCTP option is enabled in Basic Input/Output System (BIOS). Resolution To work around this problem, disable the MCTP option in BIOS and restart the system. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15015528779 False ['Multi Channel DMA for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 23.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']