Is there an issue with Skip memory initialization option in UniPHY based DDR2 SDRAM and DDR3 SDRAM Controller? - Is there an issue with Skip memory initialization option in UniPHY based DDR2 SDRAM and DDR3 SDRAM Controller? Description Yes, in the 11.0 version of the IP, Skip memory initialization option does not skip the initialization process. UniPHY based DDR2 SDRAM and DDR3 SDRAM controller does not support skipping memory initialization option. Although the IP does not skip initialization in the simulation, w hen this option is turned on, required delays between specific memory initialization commands are skipped to speed up simulation so it does help speed up the simulation. The IP GUI will be fixed to reflect the true function of this option in the future version. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']