Arria V Gen1 x8 Root Port Design Example Does Not Close Timing in 12.0 SP2 - Arria V Gen1 x8 Root Port Design Example Does Not Close Timing in 12.0 SP2 Description The Arria V Gen1 x8 Root Port Design Example might have setup time failure on the coreclkout signal in the 12.0 SP2 release of the Quartus II software. Resolution This issue is fixed in version 12.1 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']