Why does the FPGA configuration fail from Linux/U-Boot and cause the HPS to hang on Intel® Stratix® 10 SX devices when I use the phase 1 and phase 2 bitstreams with RSU enabled that are generated from different Intel® Quartus® Prime Software versions? - Why does the FPGA configuration fail from Linux/U-Boot and cause the HPS to hang on Intel® Stratix® 10 SX devices when I use the phase 1 and phase 2 bitstreams with RSU enabled that are generated from different Intel® Quartus® Prime Software versions? Description Why does the FPGA configuration fail from Linux/U-Boot and cause the HPS to hang on Intel® Stratix® 10 SX devices when I use the phase 1 and phase 2 bitstreams with RSU enabled that are generated from different Intel® Quartus® Prime Pro Edition Software versions? Mixing the phase 1 and phase 2 bitstreams that are generated from different Intel® Quartus® Prime Pro Edition Software versions is a non-supported use case. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4. Custom Fields values: ['novalue'] Troubleshooting 1508141750 False ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.4 19.3 ['Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']