Memory Presets Contain Some Incorrect Memory Timing Parameters - Memory Presets Contain Some Incorrect Memory Timing Parameters Description The memory presets contain incorrect data for the tDSa and tDHa memory timing parameters. This issue affects all configurations. Timing analysis results for write and address/command paths may be incorrect. Resolution Make sure that the memory timing parameters in the MegaWizard Plug-In Manager match the datasheet of the target memory device. The output edge rate and the use of single-ended versus differential DQS may affect certain memory parameters. This issue will be fixed in a future version of the DDR2 SDRAM Controller with ALTMEMPHY IP. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']