What is the earliest stage of compilation that I can generate a timing netlist? - What is the earliest stage of compilation that I can generate a timing netlist? Description If you are using the Intel® Quartus® Prime Pro Edition software you can create a timing netlist after the fitter plan stage, if you are using the Intel® Quartus® Prime Standard Edition software you can create a timing netlist after the analysis and synthesis stage. In the Intel Quartus Prime Standard Edition software, use this command to generate the timing netlist: create_timing_netlist -post_map Custom Fields values: ['novalue'] Troubleshooting FB: 589772; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']