Possible Internal Error with Arria V or Cyclone V Designs Using Hard Memory Controller - Possible Internal Error with Arria V or Cyclone V Designs Using Hard Memory Controller Description This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products. An internal error can occur in designs targeting Arria V or Cyclone V devices and using a hard memory controller, when the MPFE, MMR, and SC clock inputs for the hard memory controller are not driven by a PLL or by a clock buffer. Resolution The workaround for this issue is to ensure that you drive the MPFE, MMR, and SC clock inputs through a PLL. This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']