Why my design is not generated when using the third EMAC on Arria 10 SoC? - Why my design is not generated when using the third EMAC on Arria 10 SoC? Hello , We have designed a custom board which has some industrial Ethernet testing. When enabling three EMACS, the third EMAC (2) gives a warning message of invalid clock settings. Is it a known issue? anyone can help? Thanks Replies: Re: Why my design is not generated when using the third EMAC on Arria 10 SoC? Thanks FJumaah for your reply. Now it make sense. I will wait for 18.1.1. Replies: Re: Why my design is not generated when using the third EMAC on Arria 10 SoC? Hello AJuba, This is due to a bug within Platform Designer (previously Qsys). There will be a patch release in 18.1.1 Until the time of the release, you will not be able to use 3 EMACs on Arria 10. Thanks Replies: Re: Why my design is not generated when using the third EMAC on Arria 10 SoC? Anyone can help me on this?