Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_gen7_fpp_design_manager.cpp, Line: 529 - Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_gen7_fpp_design_manager.cpp, Line: 529 Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1 and earlier, you might see this internal error in the fitter plan stage when compiling an Intel® Stratix® 10 FPGA design with multiple instances of the ALTCLKCTRL Intel® FPGA IP. This error occurs when the clock gating feature is enabled and drives logic within a single I/O bank or transceiver tile. Only one clock gate is supported within a single I/O bank or transceiver tile in Intel® Stratix® 10 devices. Resolution To avoid the error, reduce the number of clock control blocks with clock gating feature enabled within a single I/O bank or transceiver tile to one. This configuration is scheduled to provide a clear error message in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting FB: 605811; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']