Why does the 2D-FIR II (4K ready) FPGA IP core return unexpected data between two output samples in simulation when using the SIEMENS* QuestaSim*? - Why does the 2D-FIR II (4K ready) FPGA IP core return unexpected data between two output samples in simulation when using the SIEMENS* QuestaSim*? Description Due to a problem with the encryption of the 2D-FIR II (4K ready) FPGA IP simulation files for the SIEMENS* QuestaSim*, unknown data will be seen between two consecutive output data when simulating the 2D-FIR II (4K ready) FPGA IP. This issue does not affect the operation in hardware. Resolution No workaround for this simulation problem exists. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16023349421 False ['2D-FIR II (4K ready) IP'] ['FPGA Dev Tools Quartus® Prime Software'] novalue 22.2 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']