Altera SoC FPGAs: Boot and Configuration - This course introduces the boot and configuration options and features available in Altera® FPGAs and SoCs. FPGA Authority is an Altera® certified trainer that provides in-depth, technically detailed instruction covering the complete FPGA and SoC design process. Training spans RTL hardware design, embedded… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® II GX FPGA Arria® II GZ FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Configuration Device EPCQ-A Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® II FPGA Cyclone® III Bare Die Cyclone® III FPGA Cyclone® III LS FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA HardCopy™ II ASIC Devices HardCopy™ III ASIC Devices MAX® 10 FPGA MAX® II CPLD MAX® II Z CPLD MAX® V CPLD Mustang Mesa Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GT FPGA Stratix® IV GX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA eASIC™ N3X Devices eASIC™ N3XS Devices eASIC™ N5X Devices easicopy™ This course introduces the configuration options and features available in Altera® FPGAs and SoCs. Choosing a configuration methodology is a critical step in any FPGA-based application. This includes selecting where configuration files will be stored, what communication channel will transfer the files, and how to protect the design IP stored in configuration memory. The course examines the full range of Altera FPGA configuration schemes — including Active Serial (AS), Passive Serial (PS), JTAG, and Fast Passive Parallel (FPP) — and covers the use of configuration devices, microprocessors, and the Altera Configuration Controller (ACC). Designers will learn to implement and validate configuration circuitry for Altera Agilex™, Stratix®, Arria®, and Cyclone® device families and construct complete boot flows from ROM to Linux® OS and Zephyr® RTOS. Topics include the Arm Trusted Firmware (ATF) boot architecture, U-Boot first-stage and second-stage bootloaders (FSBL/SSBL), device-tree configuration, driver development, secure boot, and single-image booting. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Altera SoC FPGAs: Boot and Configuration Key Features Offering Brief No No No No Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® II GX FPGA Arria® II GZ FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Configuration Device EPCQ-A Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® II FPGA Cyclone® III Bare Die Cyclone® III FPGA Cyclone® III LS FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA HardCopy™ II ASIC Devices HardCopy™ III ASIC Devices MAX® 10 FPGA MAX® II CPLD MAX® II Z CPLD MAX® V CPLD Mustang Mesa Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GT FPGA Stratix® IV GX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA eASIC™ N3X Devices eASIC™ N3XS Devices eASIC™ N5X Devices easicopy™ 2 Days No No English Offering Brief Production Windows,Linux a1JUi0000096VQXMA2 Familiarity with FPGA design flow using Quartus® Prime software Hardware and Software Engineers, FPGA Designers, SoC Developers, Verification Engineers, System Architects, Managers What's Included PDF of slides, lab manual and lab files where required Ordering Information Altera SoC FPGAs: Boot and Configuration a1JUi0000096VQXMA2 Production EDA Tools / IDE Education / Training a1MUi00000GbNhBMAV a1MUi00000GbNhBMAV Member 2026-06-08T23:36:42.000+0000 This course introduces the boot and configuration options and features available in Altera® FPGAs and SoCs. Partner Solutions