Example Design Can Fail For Certain Parameterizations of QDR II and QDR II SRAM Controller with UniPHY and DDR2 and DDR3 SDRAM Controller with UniPHY - Example Design Can Fail For Certain Parameterizations of QDR II and QDR II SRAM Controller with UniPHY and DDR2 and DDR3 SDRAM Controller with UniPHY
Description The autogenerated example design can fail for parameterizations with byteenables (data mask) disabled and burst length greater than the rate ratio. Resolution There is no workaround for this issue.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
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11.0
['Programmable Logic Devices']
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['novalue']
['novalue'] - 2021-08-25
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