Are there any known issues with the transceiver Tx signal integrity that may increase the BER on Stratix® V GX production silicon devices? - Are there any known issues with the transceiver Tx signal integrity that may increase the BER on Stratix® V GX production silicon devices? Description Yes, due to a bug in Quartus® II software versions 12.0, 12.0SP1, and 12.0SP2, you may see a periodic glitch on the transceiver Tx pins of Stratix® V GX production devices. The glitch will produce a marginal increase in Tx jitter which may result in a marginally higher Bit Error Rate (BER). Resolution To fix this problem, install the appropriate patch below. Patches for Quartus® II software version 12.0 dp2 Quartus II software version 12.0 patch 0.dp2b Windows exe file Quartus II software version 12.0 patch 0.dp2b Linux tar file Quartus II software version 12.0 patch 0.dp2b readme.txt file Patches for Quartus® II software version 12.0 dp3 Quartus II software version 12.0 patch 0.dp3e Windows exe file Quartus II software version 12.0 patch 0.dp3e Linux tar file Quartus II software version 12.0 patch 0.dp3e readme.txt file Patches for Quartus® II software version 12.0 SP1 Quartus II software version 12.0 SP1 patch 1.12 Windows exe file Quartus II software version 12.0 SP1 patch 1.12 Linux tar file Quartus II software version 12.0 SP1 patch 1.12 readme.txt file Patches for Quartus® II software version 12.0 SP2 Quartus II software version 12.0 SP2 patch 2.02 Windows exe file Quartus II software version 12.0 SP2 patch 2.02 Linux tar file Quartus II software version 12.0 SP2 patch 2.02 readme.txt file After installing the patch, regenerate your transceiver PHY and/or QSYS system and recompile your project. Custom Fields values: ['novalue'] Troubleshooting 2205971257 False ['PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Stratix® V FPGAs', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']