Why does the HDMI Intel® FPGA Source IP display flickering image after reset operation? - Why does the HDMI Intel® FPGA Source IP display flickering image after reset operation? Description Due to a problem starting in version 19.4 of the Intel® Quartus® Prime Pro software when using the Intel® Arria® 10 Devices, and version 20.4 of the Intel® Quartus® Prime Pro software when using the Intel® Stratix® 10 devices, the HDMI Intel® FPGA Source IP core may display flickering image after reset operation. This is due to a problem in the HDMI Intel® FPGA Source IP core TX auxiliary encoder design failing to re-align Start-of-Packet (SOP) with the auxiliary data. The corrupted auxiliary data causes the destination HDMI sink receiver to display a flickering image. Resolution This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 21.1 software. Custom Fields values: ['novalue'] Troubleshooting 1508828351 True ['HDMI IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 19.4 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']