Why does the EDA netlist writer not create a valid netlist for gate-level simulation of the V-Series 28 nm Hard IP for PCI Express MegaCore Function? - Why does the EDA netlist writer not create a valid netlist for gate-level simulation of the V-Series 28 nm Hard IP for PCI Express MegaCore Function? Description The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 14.1. Custom Fields values: ['novalue'] Troubleshooting 2205823238 False ['Simulation'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 14.1 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']