Why does the H2D *ST device port of the Scalable Scatter-Gather DMA FPGA IP send non-contiguous data in the DMA PCIe mode for Completion TLPs? - Why does the H2D *ST device port of the Scalable Scatter-Gather DMA FPGA IP send non-contiguous data in the DMA PCIe mode for Completion TLPs? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the Scalable Scatter-Gather DMA FPGA IP DMA PCIe Mode can only support incoming Completion TLPs for Mem Read Requests with payload lengths that aligned to the data width of the H2D *ST device port, except for the last Completion TLP where the TLP payload length equals to remaining byte count of the request. The AXI-ST Manager or Avalon-ST Source interface of the H2D device port may transmit non-contiguous data when the incoming Completion TLP payload length doesn’t meet this condition. Examples of possible combinations of 400-byte Memory Read Request Completion TLP payload length with 256-bit (32 bytes) H2D ST port data width:- Supported combinations: 256 bytes + 144 bytes, 64 bytes + 256 bytes + 80 bytes Unsupported combinations: 208 bytes + 64 bytes + 128 bytes, 144 bytes + 256 bytes Resolution There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016008464 False ['Scatter-Gather DMA Controller IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']