Enabling Periphery to Core Placement and Routing Optimization in Arria 10 designs might cause timing violations - Enabling Periphery to Core Placement and Routing Optimization in Arria 10 designs might cause timing violations
Description Timing violations might occur when you enable the Quartus ® Prime software\'s Periphery to Core Placement and Routing Optimization feature for Arria ® 10 engineering sample (ES) devices. Resolution There is no workaround. This issue will be fixed in a future release of the Quartus Prime software.
Custom Fields values:
['novalue']
Troubleshooting
FB326563;
True
['novalue']
['FPGA Dev Tools Quartus® Prime Software Pro']
16.0
15.1
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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