Why do I see redundant lvds_clk and loaden output ports when using IOPLL IP for LVDS external PLL mode? - Why do I see redundant lvds_clk and loaden output ports when using IOPLL IP for LVDS external PLL mode? Description Due to a problem in the Intel® Quartus® Prime Software version 17.1, generation of the IOPLL IP for external PLL LVDS mode results in two lvds_clk and loaden output ports. If the enable LVDS_CLK/LOADEN0 option is on, the RTL incorrectly includes five output ports. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1506795408 False ['IOPLL IP', 'LVDS SERDES IP', 'PLL'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 17.1 ['Stratix® 10 GX FPGA', 'Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-12