What is the largest capacity DDR3 device supported by the Arria® V and Cyclone® V FPGA UniPHY memory IP? - What is the largest capacity DDR3 device supported by the Arria® V and Cyclone® V FPGA UniPHY memory IP? Description There is a bug in the UniPHY DDR3 IP which incorrectly allows a configuration for a single chip select 8Gbit DDR3 memory device with 16 row, 11 column, and 3 bank address bits to be generated for the Arria® V and Cyclone® V hard and HPS memory controllers. Resolution The largest supported DDR3 device capacity configurations are as follows : Hard Memory Controller and HPS Memory Controller: 4Gbit per chip select with an address configuration of 16 rows, 10 columns, and 3 bank bits. Soft Controller: 8Gbit per chip select with an address configuration of 16 rows, 11 columns, and 3 bank bits. For further information on the Arria® V hard and HPS memory controller supported configurations, see Table 7-17: Features of the Arria® V Hard Memory Controller in the Arria V Handbook and see Table 11-1: SDRAM Controller Interface Memory Options in the Arria V Hard Processor System Technical Reference Manual. For further information on the Cyclone® V hard and HPS memory controller supported configurations, see Table 6-14: Features of the Cyclone® V Hard Memory Controller in the Cyclone V Handbook and see Table 11-1: SDRAM Controller Interface Memory Options in the Cyclone V Hard Processor System Technical Reference Manual. Custom Fields values: ['novalue'] Troubleshooting FB: 442974; False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus II Software'] 17.0 10.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']