Why is there a voltage drop in single-ended I/O standards when located on dedicated differential input pins on side I/O banks in Stratix® III devices for designs compiled in the Intel® Quartus® II software v8.0? - Why is there a voltage drop in single-ended I/O standards when located on dedicated differential input pins on side I/O banks in Stratix® III devices for designs compiled in the Intel® Quartus® II software v8.0? Description The Intel® Quartus® II Software v8.0 incorrectly enables an internal resistor between two I/Os of a side bank dedicated differential input pair when each I/O is configured as single-ended and any of the following conditions are true: The current strength is not specified The input parallel on chip termination (OCT) option for the I/O is enabled The output series OCT option for the I/O is enabled This problem affects only Stratix® III devices. If both I/Os in this pair are input-only, the internal resistor is enabled incorrectly only if the input parallel termination option for either input is enabled. This resistor may cause the I/O pin to malfunction when it is single-ended by reducing the complementary pin voltage. Resolution This problem is fixed beginning with the Intel ® Quartus ® II software v8.0 SP1. Get the latest service pack from the Download Center . To correct this problem in the Intel Quartus II Software v8.0, if you cannot upgrade to the latest service pack version, download and install patch 0.22 from the following locations: Quartus II 8.0 Patch 0.22 for PC Quartus II 8.0 Patch 0.22 for Linux Readme file for Quartus II 8.0 Patch 0.22 Custom Fields values: ['novalue'] Troubleshooting N/A False ['novalue'] ['novalue'] novalue novalue ['Stratix® III FPGAs'] ['novalue'] ['novalue'] ['novalue']